iFail: Predicting end-of-life for
future mobile devices
Dealing with test and measurement in the world of
By Timothy McMullen, Director of Product Marketing, Reliability
Test Systems, Cascade Microtech, Inc.
Consumer expectations continue to create a relentless chal- lenge for the electronics industry, demanding that each new generation of mobile devices delivers increased performance — more applications, faster speed, and longer battery
life — all without sacrificing reliability. To capture their share of
the multi-billion dollar mobile electronics market, manufacturers
are under great pressure to produce innovative, next-generation
products as inexpensively and as quickly as possible.
Pushing the performance and time-to-market envelopes often
runs counter to the concept of conservative designs with built-in quality and reliability. To meet performance and cost goals,
device manufacturers are forced to pursue creative new technologies such as FinFETs (3D transistors) and 3D IC integration
schemes with bumps, pillars,
and through-silicon vias (TSVs).
But these new design approaches
can have serious implications on
semiconductor device life and
reliability. This is where intrinsic
semiconductor reliability testing
comes into play, enabling designers to find the sweet spot that
optimizes both performance and
quality while keeping to a quick
What is reliability testing?
Intrinsic reliability testing pre-
dicts the long-term viability
(Figure 1) of ICs by measuring
the wear-out proper-
ties of the materials
used in manufacturing.
design specialized test
structures on the wafer
and subject them to a
variety of elevated electrical and thermal biases
to accelerate their breakdown. Data from these
tests are extrapolated to
estimate IC life under
normal use conditions, and the results of this evaluation inform
decisions to qualify fabrication lines and determine safe operating condition rules for IC designers.
Trends impacting reliability test
For decades, shrinking semiconductor device size was the prima-
ry mechanism for achieving performance and cost goals accord-
ing to “Moore’s Law.” Years
of innovations have driven
minimum feature sizes from
several microns in the 1980s
down to 22 nm in current
production, with roadmaps
to 5 nm and beyond.
However, simple scaling
is reaching practical limita-
tions (Figure 2); to continue
ductor manufacturers have
introduced exotic materi-
als, processing techniques,
and structure types (or
“More Moore” technolo-
gies) including ultra-low-k
intra-level dielectrics (ILDs)
Figure 2. Semiconductor trends affecting reliability.
Figure 1. “Bathtub curve” illustrating
the realm of intrinsic reliability consideration.