By Mike Dewey, Director of Marketing, Marvin Test Solutions
Continual advancements request higher demand for digital test system performance, which present new power requirements and
Digital functional test systems have been part of the test landscape for over 40 years. The earliest test
systems employed simple, static digital test capabilities.
However, as the performance and complexity of these
digital devices, modules, and systems evolved, the digital
test instrumentation advanced as well. In particular, the
on-going advancements associated with device toggle
rates have placed a corresponding demand for ever-higher
performance on the test instrumentation and systems,
with today’s high-end semiconductor test systems
offering multi-GHz test capabilities with attendant high
For military-aerospace applications, digital functional
test has always presented a unique set of requirements
and challenges. Unlike the test requirements associated
with high-end device test, M-A applications are primarily
focused on supporting module and system level test.
Consequently, “bleeding edge” digital test performance
is not required; however, a broad range of test flexibility
and capability is required. The test systems and associated
digital subsystems are tasked with supporting a broad
portfolio of both legacy and current generation electronic
assemblies, since these test systems are being used to
service products in the field as well as test new generation
products in the factory. More specifically, test systems
deployed in the field (such as the VIPER/T shown in
Figure 1) have the added constraints of both size and
power dissipation – with the requirement that these
systems be portable and exhibit high reliability.
Figure 1: VIPER/T Test System.
The digital subsystem’s capabilities associated with
these types of systems include:
• Support vector rates of at least 50 MHz with timing
per pin, multiple time sets, and a flexible sequencer.
• Offer a compact footprint and modular architecture,
• Offer a wide programmable drive / sense voltage
range, which allows support for both legacy
applications as well as current technologies.
• Flexible architecture providing per pin
programmability – maximizing flexibility for a wide
range of applications.
Managing the power requirements and power
dissipation associated with these digital subsystems is
a key requirement to achieving high reliability. Modern
digital subsystems employ two major components - a
high performance ASIC or FPGA which provides all
of the digital logic, timing, and sequence control; and a
monolithic pin electronics (PE) device(s) which interfaces
to the digital logic and provides the programmable levels
to the UUT or device under test (Figure 2).
Figure 2: Digital Subsystem Architecture.
Historically, pin electronics for digital subsystems
have relied upon custom designs – some discrete, some
hybrid, and some full custom. However, today there are
commercial vendors producing a range of pin electronic
products for both semiconductor and board level test
applications that offer a high level of integration and
channel density. These devices are a key enabler to
achieving ever higher channel densities, which also
brings with it the on-going challenge of managing power
dissipation and power consumption.
Today’s digital subsystems are based on open
architecture, card modular platforms such as the VXI and
PXI standard, with PXI being the dominant platform.
And to accommodate many of the necessary features and
capabilities associated with supporting M-A applications,
PXI’s 6U form factor offers added PCB real estate and
flexibility with regard to the use of additional power
supplies, beyond the standard PXI supplies. However,
power management is still a primary concern for these
06/2017 • www.ECNmag.com