with various interconnect barrier metals, hafnium-based high-k/
metal-gate (HKMG) dielectric gate stacks, and the highly-publi-cized FinFET transistor structures. IC makers are also introducing
game-changing “More than Moore” structural advances such as
3D IC integration schemes that stack multiple dies using solder
bumps, copper pillars, and TSVs.
As this drive for innovative solutions continues, and as new
technology nodes increasingly diverge from their predecessors,
the associated uncertainties must be met with careful reliability
testing. These technologies require more from reliability test
equipment — new test algorithms, tighter source and measurement accuracy, faster data sampling, and higher test throughput
— to bring new technologies to market faster.
Reliability engineers are also shifting away from the traditional
package level reliability (PLR) program toward increasing reliance
on wafer level reliability (WLR). For PLR, DUTs are sawn from
the wafer, individually packaged, and tested in temperature
chambers. WLR uses probe stations and thermal chucks to directly
test DUTs on intact wafers. PLR remains an essential element of
reliability test programs, but the increased interest in the WLR
approach is due to faster initial test results, elimination of DUT
damage from handling, and lower operating cost, and is further
enabled by the capabilities of today’s parallel WLR systems.
Key reliability test applications
Intrinsic reliability test applications are often segregated between
back-end-of-line (BEOL) and front-end-of-line (FEOL). Some of
the most common IC failure modes are electromigration (EM), bias
temperature stress (BTS), time-dependent dielectric breakdown
(TDDB), and bias temperature instability (BTI).
Electron flow through metal over time causes atoms to dislo-
cate (electromigration), creating voids and extrusions in copper
lines and vias, solder bumps, and TSVs. This results in high-
resistance connections, localized hot spots, and short-circuits
to nearby features causing IC failure. EM tests are most com-
monly performed as PLR, and modern EM test systems utilize
source-measurement unit (SMU) designs with fast measurement
sampling, ultra-low-resistance measurement abilities, and ul-
tra-low-current source accuracy.
Ultra-low-k ILDs and barrier layers are targets for bias temperature stress, where an electric field induces barrier layer
breach and Cu oxidation, and ultimately short-circuited connections. Time-dependent dielectric breakdown in transistors, including those based on HKMG and FinFET technology, responds
to the electric field across the gate oxide with the creation of
charge traps that permit current to tunnel through the insulator.
This leads to transistor performance shifts and short circuits. BTS
and TDDB are often tested with the same equipment, and today’s
systems employ faster sampling and better measurement accuracy
to clearly detect and interpret soft breakdown (SBD) and progressive breakdown (PBD) phenomena. These tests are efficiently
performed with both PLR and WLR.
Bias temperature instability is a pressing concern for advanced
geometry CMOS transistors, and it results in shifting transistor performance. BTI is believed to occur primarily at the silicon-insulator
interface; thin HKMG transistors and especially FinFETs are most
likely to experience BTI. BTI includes a transient component that
self-heals rapidly after stress is removed from the device, and new
test algorithms called “on the fly” or “ultra fast” minimize stress
disruptions by using fast equipment and simple measurements to
estimate device wear-out rather than directly measure it. Currently,
BTI is performed almost exclusively as a WLR test.
Today’s IC manufacturers are drawing increasingly finer lines
between reliability and performance. It is no longer sufficient to
qualify semiconductor lines with a simple pass/fail evaluation.
Many IC designers are fine-tuning and optimizing the reliability-versus-performance balance for each individual subsystem within
their chips. The delicacy of this balance drives the increased use
of WLR and more stringent demands upon reliability test equipment for precision and throughput. Advanced test tools are key
to the semiconductor industry’s campaign to bring more sophisticated, reliable mobile products to market faster. ECN
The challenge of avoiding system failures in
increasingly complex components
By Taqi Mohiuddin, Senior Director, Marketing,
Evans Analytical Group (EAG)
Failures have increasingly serious consequences as today’s electronics systems become smaller, more complex and more deeply embedded in our daily lives. System failures must be
found and fixed before they can cause costly downtime, product
recalls and reputational damage. This requires a comprehensive,
Reducing system failure costs
multi-disciplinary approach to electronics system failure analysis
that includes specialized tools and expertise.
System complexity is not only increasing at the board level,
but at the IC, package and die level, as well. Process technology
advances have taken us to devices containing billions of transistors, and many previously discrete components and independent
subsystems are now being integrated. We also continue to see
the rapid miniaturization of electronic components using FinFET,
metal gate, low-k dielectric and other advanced process nodes.
Additionally, we are using more complex packages including SIP,
MCM, SiSub, stacked die, TSV and Cu wire, along with more
complex package and board materials, as well as coatings and