integrity issues in cloud
While the cloud promises to reduce nterprise network infrastructure and operating costs, the remote execution of
applications makes factors such as latency, performance, and reliability critical considerations
in the design and deployment of cloud computing platforms. A key factor determining server
performance, cloud or not, is maintaining a bit
error rate (BER) on the order of 1.E- 12 for the overall system.
Given that a single bit error can necessitate the resending of
an entire packet, real-time data performance drops sharply as the
Data travels over numerous high-speed interfaces as it passes
through the cloud, and poor signal integrity over any of these interfaces is a leading cause for undesirable BER degradation. Thus,
as data rates continue to increase, assuring proper signal integrity
through the signal channel becomes critical. However, the long
trace distances inherent in data center equipment make maintaining signal integrity challenging.
For example, consider a typical server chipset integrating a
PCI Express Gen 3 controller with a maximum channel loss spec
of 20 dB. At Gen 3’s signaling rate of 8 Gbps, maximum trace
length, given FR4 PCB losses, typically equates to approximately
18”, less with connections and vias. Server motherboards have
a deep form factor, however, and include many other sources of
attenuation, including multiple connectors and vias that reduce
signal integrity and the length over which traces can be driven
reliably (see Figure 1). It is also not uncommon for server manu-
Figure 2. In a real-world server, the complete signal channel can exceed the interface specifications by a large margin. Signal conditioning can restore signal integrity by applying equalization to received
signals and pre-emphasis when redriving or repeating signals to compensate for expected channel losses. This allows designers to drive
signals further than otherwise possible while still using cost-effective
FR4 PCB materials.
switch fabric. Switches must pass high-speed, 10 Gbps Ethernet
signals across the backplane and multiple connectors. Some traces
within the switch fabric may run quite long, exceeding the chipset or endpoint’s maximum drive capability. A similar situation
arises with storage applications using 12 Gbps SAS.
Figure 1. A typical PCI Express Gen 3 server blade will have multiple
vias, traces, and a connector through which the signal must travel.
As shown by the two test points, signal conditioning restores signal
integrity to open the signal eye and compensate for channel losses to
keep a signal within the specified limits of the interface.
facturers to include mid-plane and daughtercard connectors in
the channel path to support different product line options. When
this connector is not populated, it has a jumper inserted instead,
and the resulting signal path, with all of its sources of loss, is
likely to push beyond the specified limits of the interface.
Restoring signal integrity
Jitter, and the attenuation it results in, is one of the leading
causes of signal loss in server applications. There are two basic
types of jitter: random and deterministic. Random jitter arises
mainly from the clock source as any jitter in the clock will be
reflected in every signal associated with that clock. Deterministic
jitter is generated primarily by a channel’s characteristics and
builds cumulatively as more connectors, vias, and trace lengths
are added to the channel.
There are several ways to address signal loss, either by reducing losses or actively restoring signal integrity. Designers can
reduce losses by limiting the sources of jitter and attenuation in
the system. Two common methods used to achieve this are using
a board material that has lower losses than FR4 and by adjusting
layout guidelines to use wider traces.
More exotic board materials, while better preserving signal integrity, are more expensive than FR4. In addition, they unnecessarily increase system cost across the entire motherboard, not just
for those signals that need added margin. Widening traces also
has limited application, given that the motherboard, although
large, is already crowded with components.
Alternatively, designers can address signal loss by restoring and
boosting signal integrity using active components like redrivers